FIG. 10 is a cross-sectional constructional diagram of a MOSFET constituting a power semiconductor element employed in the output stage of a prior art intelligent switching device. In FIG. 10, an n well region 2 is formed at the surface of a p type semiconductor substrate 1 and a p well region 3 is formed at the surface of the n well region 2. An n+ source region 4 and n+ drain region 5 are formed at the surface of the p well region 3. In addition, a structure that moderates the electrical field of the PN junction between the n+ drain region 5 and p well region 3 is provided by forming an n offset region 6 of comparatively low concentration surrounding the n+ drain region 5. A gate electrode 8 is formed on the other side of a gate oxide film 7 at the surface of the p well region 3 that is sandwiched by the n+ source region 4 and the n offset region 6. A LOCOS oxide film 19 that is thicker than the gate oxide film 7 is formed at the edge of the gate electrode 8 on the drain side, with the object of moderating the electrical field directly below the gate electrode at the side edge. Also, a p+ contact region 9 is formed at the surface of the p well region 3 adjacent to the n+ source region 4 and is connected to a source electrode 10 in common with the n+ source region 4. In addition, an n+ contact region 12 is formed at the surface of the n well region 2 and is connected with an n well electrode 13.
In such a construction, since the p well region and n well region are both separated from the substrate by a PN junction, there is a high degree of freedom of design in regard to source potential and drain potential, and the construction is applicable to intelligent switching devices, in particular to applications having MOSFETs with a plurality of output stages, where the source potentials and drain potentials thereof are different. It should be noted that, although interlayer insulating films are provided between electrodes of different potential, such as between the gate electrode 8 and the source electrode 10, they are not shown in the following drawings.
Sometimes (see for example Laid-open Japanese Patent Publication Number H. 10-284731) parasitic action of the body diode of a MOSFET is suppressed by providing an embedded n+ region on a p substrate, providing an n epitaxial layer on top of that region, forming a Schottky barrier diode in this portion, and connecting it parallel in the same region with the body diode of the MOSFET.
Also, parasitic action of the body diode may be suppressed (see for example U.S. Pat. No. 4,811,065) by forming a Schottky barrier diode on the surface of the substrate (drain) region of the MOSFET, and connecting it parallel on the same chip with the body diode of the MOSFET.
FIG. 10 is an application circuit diagram of an intelligent switching device comprising a MOSFET with an output stage having a construction as shown in FIG. 9 mentioned above. FIG. 10 is a single phase bridge circuit construction, in which two MOSFETs Q3 and Q1 are connected in series between the power source potential Vcc and reference potential GND and two series-connected MOSFETs Q4 and Q2 are connected in parallel therewith. The load is connected between the connection point of MOSFET Q3 and MOSFET Q1 and the connection point of MOSFETs Q4 and MOSFET Q2; alternate switching between MOSFET Q1 and MOSFETs Q4 on the one hand, and MOSFET Q2 and MOSFET Q3 on the other hand is performed by supplying a signal from a drive circuit, not shown. By means of this switching, current can be made to flow in the load from left to right or in the opposite direction. Commonly, in such a circuit, the load is an inductive load such as a motor. However, in the case of an inductive load, if MOSFETs are employed having the complicated connection structure shown in FIG. 9, problems tend to arise due to parasitic effects.
FIG. 11 is a view given in explanation of the parasitic effects when a MOSFET according to FIG. 9 is used for MOSFET Q1 or MOSFET Q2. In FIG. 11, the condition where MOSFET Q3 or MOSFET Q4 are ON corresponds to the case where the n well region 2 of MOSFET Q1 or MOSFET Q2 is connected with Vcc, which is the highest potential. For simplicity of illustration of FIG. 11, the n offset region 6 and LOCOS oxide film 19, etc., shown in FIG. 9 are omitted.
Referring to FIG. 10, while MOSFET Q3 and MOSFET Q2 are ON so that current flows from the left-hand side to the right-hand side of the load (inductive load), if MOSFET Q3 is cut off, an e.m.f. trying to keep the current flowing in the inductive load is generated, causing the potential of the point of connection of MOSFET Q1 and MOSFET Q3 to become lower than the reference potential GND.
In FIG. 11, when the drain electrode 11 with respect to the source electrode 10 connected to GND potential becomes lower than the threshold voltage (˜0.7 V) of the PN junction, the p well region 3 and the PN junction of the n+ drain region 5 is forward-biased, causing base current to flow in the parasitic transistor Qp1 constituted by the n well region 2, the p well region 3 and the n+ drain region 5, causing the collector current of the parasitic transistor Qp1 to flow from Vcc toward the load. FIG. 13 shows this in the form of an equivalent circuit, in which the parasitic transistor Qp1 of FIG. 10 is added as a parasitic transistor Qp and a collector current Ic flows in accordance with the base current Ib.
Furthermore, with a MOSFET of this construction, it is also possible to connect the n well region 2 and drain region 5 by common wiring. FIG. 12 is a view given in explanation of the parasitic effect in this case. In this case, since the n well region 2-1 and the drain region 5 are at the same potential, the parasitic NPN transistor Qp1 in FIG. 11 is basically inactive. However, the PN junction between the p well region 3 and the drain region 5 and the PN junctions between the p well region 3 and the n well region 2-1 and between the p substrate 1 and n well region 2-1 are forward-biased. For example, if a MOSFET n well region 2-2, etc., is present on the high potential side, such as of MOSFET Q3 or MOSFET Q4, etc., in the vicinity of MOSFET Q1, a base current flows in the NPN parasitic transistor Qp2 shown as Qp2 in the FIG., and this parasitic transistor Qp2 is turned ON. If this is illustrated by an equivalent circuit, in the same way as in the case of FIG. 11, Qp2 corresponds to Qp of FIG. 13, and collector current flows from Vcc to the load.
Next, FIG. 14 is a view given in explanation of the parasitic effect produced in a MOSFET on the high potential side such as MOSFET Q3 or MOSFET Q4. In this case, since the drain of the MOSFET on the high potential side is connected with Vcc, which is the highest potential, a connection construction as shown in FIG. 14 is produced, in which the n well region 2 and drain region 5 are normally connected. First, in the circuit to FIG. 10, while MOSFET Q4 and MOSFET Q1 are ON so that current flows from the left-hand side to the right-hand side of the load, if MOSFET Q1 is cut off, an e.m.f. is generated such as to try to keep the current flowing in the inductive load, so that the source potential of the MOSFET Q3 becomes higher than Vcc. Consequently, in FIG. 14, the PN junctions between the p well region 3 and drain region 5 and between the p well region 3 and n well region 2 are forward-biased so that a base current Ib of the parasitic transistor Qp3 of the PNP in FIG. 14 flows, so that the parasitic transistor Qp3 is turned ON, causing current to flow from the load to GND. The equivalent circuit of this is shown in FIG. 15.
When such a parasitic effect is produced by parasitic transistors, not only can element destruction occur due to current concentration on reverse recovery of the PN junction of minority carriers generated by forward-biasing of the PN junction, but also there is the problem of latching up easily occurring due to various parasitic elements which exist in CMOS circuit for example.